Digital VerificationIndustry standard methodology to ensure a bug free product with proper functionality at the end.
Digital Verification (DV)Neural Semiconductor Digital Verification Team has the capability and right skillset to verify your design or chip through industry standard methodology to ensure bug free product with proper functionality at the end. We’re familiar with architectures like RISCV both single core and multi core, GIC, DM, DMA etc. We have first-hand experience with the verification of bus systems like AXI, APB, AHB, and Wishbone and peripherals like UART, SPI, I2C, GPIO etcWe’ve the expertise of developing Testbench in both C and SystemVerilog language for both UVM methodology and custom flow based on customer requirements aiming for coverage driven.
Digital Verification Competency- Block level, IP level and Full-chip verification using SystemVerilog, UVM methodology
- Testbench and Testcases Development having self-checking features
- Development of agent, monitor, driver and sequencer in UVM methodology
- Coverage driven, directed and assertion based SoC verification
- Constraint randomization based SoC verification
- Gate Level Simulation (GLS)
- Low Power Verification using CPF & UPF flow
- Architecture exposure on single & multi core RISCV, GIC, DM & DMA
- Bus system verification exposure of AXI, APB, AHB, Wishbone.
- Peripheral verification of UART, SPI, I2C, GPIO
- C/C++ model based SoC Simulator Development
- Programming Proficiency: Verilog, SystemVerilog, Assembly, C, C++, Python. Tcl
